Computers from the earliest times have generally performed better with more and faster random access memory (RAM). Indeed, an ideal computer would have an unlimited amount of fast RAM. In reality however, RAM has been one of the more expensive components in a computer system. The cost of a computer system escalates with the amount and speed of the RAM.
An economical solution, which most computer systems typically implement, is a memory hierarchy scheme. The memory hierarchy scheme is based on the principle that programs tend to reference a relatively confined area of memory repeatedly within a given period of time. This principle of locality encompasses two types of locality: spatial locality and temporal locality. Spatial locality refers to accessing addresses in the neighborhood of a once referenced address. On the other hand, temporal locality refers to accessing the once referenced address repeatedly.
The caching scheme implements the memory hierarchy scheme in the vast majority of computer systems today. The caching scheme utilizes a fast and small memory in combination with a slow and large memory. In general, the slow and large memory (e.g., main memory) implements dynamic RAM (DRAM) technology while the fast and small memory uses synchronous static RAM (SRAM) technology. The faster and smaller memory is often called the cache memory. Using the principle of locality, the caching scheme operates by loading data into the fast cache memory infrequently and accessing the loaded data many times before replacing the data with a new set of data. Caching schemes for loading and replacing data are well known in the art.
In general, the SRAM is typically implemented in an integrated circuit (IC) chip. The SRAM contains the actual memory cell array and circuits for synchronously accessing the data in the array. In order to load or access data in the array however, the SRAM must be provided with an address to the data to be loaded or accessed. In addition, the SRAM must be provided with control signals to latch the address synchronously at a precise time.
Conventional synchronous SRAM chips typically require three control signals to latch the address of a new clock cycle. For example, the SRAM, IDT71V433, manufactured by Integrated Device Technology, Inc. is a 3.3V high speed 1,048,576-bit SRAM organized as 32K.times.32 bit memory array including a full support of various processor interfaces to processors such as the Pentium.TM. (from Intel Corporation) and PowerPC.TM.. The IDT71V433 requires three control signals: ADSP.sub.--, ADSC.sub.--, and CE.sub.--.
Prior Art FIG. 1A illustrates a block diagram of a caching system 100 illustrating how a SRAM 104 latches an address using three control signals. A processor 102 issues an address 112 of a data 114 to be accessed and activates an address status signal ADS.sub.--. The address 112, data 114, and address status signal ADS.sub.-- 116 are put on address bus 108, data bus 110, and control bus line 118, respectively, for transmission. A controller, or control circuit 106 receives the address 112 and address status signal 116 on line 118.
The controller 106 generates an address status signal ADSC.sub.-- and transmits it to SRAM 104 over control bus line 120. The controller circuit 106 also generates a chip enable signal CE.sub.-- for enabling the SRAM 104. The chip enable signal CE.sub.-- is transmitted to SRAM 104 over control bus line 122.
The SRAM is coupled to the address bus 108 to receive an address to be latched. The data bus 110 is coupled to the SRAM to transmit data to and from the SRAM. The SRAM 104 receives three control signals for latching an address of a new clock cycle: the address status signal ADSP.sub.--, the address status signal ADSC.sub.--, and the chip enable signal CE.sub.--. The processor 102 generates and provides the address status signal ADSP.sub.--. On the other hand, the controller 106 generates and provides the address status signal ADSC.sub.-- and chip enable signal CE.sub.--. The controller 106 typically generates the address status signal ADSC.sub.-- for accessing the main memory 208 for load/store operations. In this configuration, the SRAM 104 latches a new address when the chip enable signal is active and either of the address status signals ADSC.sub.-- or ADSP.sub.-- are active. The latching of the new address is synchronized to a system clock.
Prior Art FIG. 1B illustrates a timing diagram 150 of the signals in the caching system for latching an address. A system clock provides a reference clock signal cpuclk 152 to synchronize the control signals in latching the address. The timing diagram 150 shows reference clock cycles, from 0 to 8. The SRAM 104 latches a new address on the rising edge of the system clock when the chip enable signal is sampled active low and either of the address status signals ADSP.sub.-- or ADSC.sub.-- is sampled active low. For example, as indicated by timing diagram 160, the SRAM 104 latches a new address at beginning of the clock cycle 1 when both address status signals ADSP.sub.-- and ADSC.sub.-- are active low and when the chip enable signal CE.sub.-- is active low. On the other hand, the SRAM 104 latches a new address at the beginning of clock cycle 6 as the address status signal ADSC.sub.-- and, chip enable signal CE.sub.-- are active low. The control circuit 106 activates the address status signal ADSC.sub.-- for accessing the main memory 208 for read/write (i.e., load/store) operations.
Unfortunately, the address latching mechanism illustrated in FIGS. 1A and 1B presents several drawbacks. First, wiring the address status signal ADS.sub.-- from the processor 102 to the SRAM 104 leads to narrower time margins for the control circuit 106 chip sets. This is because the address status signal ADS.sub.-- from the processor 102 is usually a time critical signal. Second, having an extra address status signal ADSP.sub.-- that can start a latching cycle in the SRAM leads to more complex controller circuit 106 circuitry. In addition, driving two control signals, the address status signal ADSC.sub.-- and CE.sub.--, from the controller 106 to the SRAM further complicates the design of the controller 106 circuitry.
Thus, what is needed is a method and system for latching an address into a SRAM without driving an address status signal from the processor to the SRAM. What is further needed is a method and system that can latch the address into the SRAM without driving two control signals. The present invention satisfies these needs by providing control circuitry that drives only one control signal into the SRAM while inactivating the address status signal ADSP.sub.-- on the SRAM.